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Get2Chip DAC Benchmark Challenge Proves Its Synthesis 30X Faster, With Better Quality Than Competition
SAN JOSE, Calif.--(BUSINESS WIRE)--June 29, 2001--Synthesis
technology leader Get2Chip today announced the results of its ``Dare To
Compare'' benchmark challenge that pitted Get2Chip tools against
unnamed competitors in a series of head-to-head comparisons during
last week's Design Automation Conference (DAC) in Las Vegas, Nev.
``We are quite pleased with the outcome of these direct
comparisons,'' said Bernd Braune, Get2Chip president and CEO. ``As our
customers have already learned, Get2Chip's architectural/RTL synthesis
provides a better alternative capable of producing superior results in
a much shorter time.''
Throughout its DAC challenge, the company invited chip designers
to benchmark their synthesis results against Get2Chip live, during the
show. Results of the challenge -- comparing the runtime and quality of
results obtained with Get2Chip synthesis solutions against those of
competing companies -- were posted daily in the Get2Chip booth, and
are summarized below:
Monday, June 18, Networking Design -- RTL Synthesis
Competitor G2C Improvement
Speed 385MHz 474MHz 23 percent better
Size 550,000 gates 490,000gates 11 percent smaller
Run-Time 43:30hours 1:25hours 30x faster
Library 0.18 TSMC 0.18 TSMC
Tuesday, June 19, Telecom Design -- Architectural Synthesis
Competitor G2C Improvement
Speed 140MHz 200MHz 30 percent better
Size 310,000 gates 250,000gates 20 percent smaller
Run-Time 13:00hours 2:30hours 6x faster
Library 0.18 TSMC 0.18 TSMC
Wednesday, June 20, Networking Design -- RTL Synthesis
Competitor G2C Improvement
Speed 226MHz 298MHz 32 percent better
Size 1,115,000 gates 976,000gates 12 percent smaller
Run-Time 63:00hours 6:15hours 10x faster
Library 0.18 TSMC 0.18 TSMC
About Get2Chip
Get2Chip, Inc., was launched in early 2000 by semiconductor
veterans and chip design tool experts from LSI Logic, VLSI Technology,
Synopsys (Nasdaq: SNPS) and Mentor Graphics Corporation (Nasdaq: MENT - ). Its breakthrough front-end tool suite, VOLARE(TM), provides
fully integrated, multi-level synthesis that offers the flexibility to
do chip design at the architectural, register transfer (RTL) or gate
level. VOLARE has been developed for complex SOC designs in ultra-deep
submicron silicon technology, targeted toward networking and
telecommunications, wireless communications and multimedia
applications. Its TOPOMO(TM)integrates and automates block
partitioning, block placement, global routing and synthesis into one
front-end integrated circuit (IC) design tool. Get2Chip is privately
held and has development centers in San Jose, Calif., and Munich,
Germany. Corporate headquarters: 2107 North First Street, Suite 350,
San Jose, Calif. 95131. Telephone: (408) 501-9600. Facsimile: (408)
501-9610. Email: info@get2chip.com. Web Site: http://www.get2chip.com.
Get2Chip, VOLARE and TOPOMO are trademarks of Get2Chip. Get2Chip
acknowledges trademarks or registered trademarks of other
organizations for their respective products and services.
Contact:
Public Relations for Get2Chip
Nanette Collins
(617) 437-1822
nanette@nvc.com
or
Jim Lochmiller
(541) 552-0616
lochpr@yahoo.com
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